1. Field
The present general inventive concepts described herein relate to a semiconductor memory device.
2. Description of the Related Art
In a conventional flash memory, a tunnel oxide layer deteriorates due to a plurality of write operations. Deterioration of the tunnel oxide layer causes a loss of a storage characteristic of a memory element (memory cell transistor) while data is stored therein, thereby increasing an error rate: a rate in which error bits are generated. In particular, in a NAND flash memory, the error rate may increase with an increase in a capacity of a memory cell, that is, scaling of a fabricating process. For this reason, at a write operation, redundancy data (parity data) of an error correcting code (ECC) (hereinafter, referred to as ECC redundancy data) is added to data to be stored, and resultant data is stored in a flash memory as a data stream. At a read operation, data that includes an error bit(s) is corrected using the ECC redundancy data. For example, a semiconductor memory device including an ECC circuit to perform ECC processing is disclosed in a patent reference 1 (Japanese Patent H11-242899).
Also, in the NAND flash memory, a test operation is performed just after fabrication to detect various cases: a bit fault that makes it impossible to store data, a short circuit that a bit line connected to a memory cell transistor is connected with another bit line, and a bit line open phenomenon. In these cases, data of a memory cell transistor is latched via a bit line, amplified, and output to an external device, or a set of a page buffer to write data at a memory cell, a bit line connected to the page buffer, and a memory cell transistor connected to the bit line is replaced with a defect-free set. To replace a defective set with a defect-free set is referred to as a redundancy technique. However, in the semiconductor memory device disclosed in the patent reference 1, a defective bit is repaired using ECC processing without replacing a defect using the redundancy technique. In this manner, however, a correction processing capacity of ECC processing to repair a memory cell transistor with no data storage characteristic due to its inherent aging is consumed to repair a defective bit due to a fabrication process, thereby lowering the correction processing capacity of ECC processing.
For the above-described reason, today, repairing a defective bit and correcting an error using ECC processing are made independently as will be described later.
FIG. 17 is a diagram schematically illustrating a typical block configuration of a NAND flash memory. In a NAND flash memory 80 illustrated in FIG. 17, a NAND controller (memory controller) 90 disposed outside of the NAND flash memory 80 executes ECC processing.
The NAND flash memory 80 in FIG. 17 contains a memory array 101, a page buffer 82, a column coding circuit 83, a column repair multiplexer (hereinafter, referred to as a column repair circuit) 84, and an I/O PAD 106.
Also, the NAND controller 90 has an ECC engine (ECC circuit) 87 and an I/O PAD 106c. 
The memory array 101 includes a plurality of memory cell transistors, each of which stores 1-bit data. In the memory array 101, memory cell transistors connected to the same word line constitute a page. Data is written at or read from memory cell transistors in a page at the same time.
The page buffer 82 is configured to store data bits the number of which is equal to the number of memory cell transistors in a page of the memory cell array 101. FIG. 18 is a diagram illustrating a page buffer unit of a page buffer 82. Also, FIG. 19 is a diagram illustrating an internal circuit configuration of a conventional page buffer unit.
The page buffer 82 consists of a plurality of page buffer units, each of which is configured as illustrated in FIG. 18. The page buffer unit includes bit circuits 51_0a to 51_7a, each of which is connected to one bit line and stores data read from a memory cell via a bit line or data to be written at a memory cell via the bit line.
When receiving a column address signal Sub BL Coding from a column coding circuit 83 illustrated in FIG. 17, a multiplexer 52_b selects one of the bit circuits 51_0a through 51_7a based on a column address signal (DIO<i> in FIG. 19). That is, the multiplexer 52_b connects one of eight bit lines to a PB control circuit 83_1.
Receiving a column address signal Coding from the column coding circuit 83 illustrated in FIG. 17, the PB control circuit 83_1 connects a bit circuit selected by the multiplexer 52_b to a peripheral circuit via a data bus Data Bus_1.
With the above-described configuration, each memory cell transistor in a page is connected to a bit line of the page buffer 82 via a bit line. One, selected by a column address, from among the bit lines is connected to a data bus, so data is written at or read from a memory cell.
Returning to FIG. 17, the column coding circuit 83 generates the column address signals Sub BL Coding and Coding (refer to FIG. 18) based on a column address from an address control circuit (not illustrated) and selects a page buffer unit of the page buffer 82 corresponding to the column address signal. Accordingly, data is written at a memory cell transistor via the I/O pad 106, data buses Data Bus_2 and Data Bus_1, a bit circuit, and a bit line. Also, data is read from a memory cell via a bit line, a bit line, the data buses Data Bus_2 and Data Bus_1, and the I/O pad 106.
Also, the page buffer 82, as illustrated in FIG. 17, is formed of page buffers 82a and 82b. The page buffer 82a amplifies a potential of a bit line connected to a normal memory cell and latches the amplified result. The page buffer 82b is a page buffer that is replaced together with a normal memory cell and a bit line when a memory cell or a bit line connected to the page buffer 82a are defective. That is, if one of page buffer units of the page buffer 82a is defective, then it is repaired with one of page buffer units of the page buffer 82b. 
The column repair circuit 84 is configured to repair a defective page buffer unit with a page buffer unit of the page buffer 82b. For example, the column repair circuit 84 controls the column coding circuit 83 when a column address indicating a location of a defective page buffer is received at a data read operation on a memory cell transistor. That is, under a control of the column repair circuit 84, a page buffer unit of the page buffer 82b is selected instead of a defective page buffer unit of the page buffer 82a. Thus, data in a selected page buffer unit is read out to a peripheral circuit via the data buses Data Bus_2 and Data Bus_1 and the I/O pad 106. A column address indicating a location of a defective page buffer includes repair information illustrated in FIG. 17. The repair information is detected via a semiconductor tester device (memory tester) during a test operation after fabrication and then is stored in a system storage area of a memory array 101, for example, before shipping.
Meanwhile, when a column address indicating a location of a defective page buffer is received at a data write operation on a memory cell transistor, the column repair circuit 84 controls the column coding circuit 83 such that a page buffer unit of the page buffer 82b is selected instead of a defective page buffer unit of the page buffer 82a. Thus, data from the I/O pad is provided via the data buses Data Bus_2 and Data Bus_1 to a page buffer unit of the page buffer 82b, not a defective page buffer unit.
The data buses Data Bus_1 and Data Bus_2 are wirings to transfer data between the page buffer 82 and the I/O pad 106 and are formed of 8 or 16 lines. The I/O pad (or, interface unit) 106 is an external terminal to transfer data between the NAND flash memory 80 and the NAND controller 90.
An I/O pad (or, interface unit) 106c of the NAND controller 90 is an external terminal to transfer data between the NAND flash memory 80 and the NAND controller 90.
At a data read operation of the NAND flash memory 80, the ECC engine (ECC circuit) 87 receives data (including data before repairing, but probability that the data includes an error exists) from the NAND flash memory 80 via the I/O pad (or, interface unit) 106c. The ECC circuit 87 performing ECC processing (decode processing) on the received data based on, for example, parity data stored therein and outputs clear data after error correction to an external device. Meanwhile, at a data write operation of the NAND flash memory 80, the ECC circuit 87 generates parity data from data received from an external device and 1-page data of the NAND flash memory 80 before the received data is written. The ECC circuit 87 stores the parity data therein and outputs write-in data to the NAND flash memory 80 via the I/O pad (or, interface unit) 106c. 
As described above, in a typical NAND flash memory, ECC processing is executed at an external device. For this reason, data when the ECC processing is performed is data that passes through the column repair circuit 84, that is, data after defective column repairing.
A time for the ECC processing is required because the NAND flash memory 80 sends data only using a bus width of the I/O pad 106 at the ECC processing. To widen a bus width at the ECC processing is considered to shorten a time for the ECC processing. For example, there is considered to widen bus widths of the data buses Data Bus_1 and Data Bus_2 of the NAND flash memory 80.
However, if a bus width is doubled, the size of the column repair circuit 84 is also doubled to maintain a repair efficiency of defective bits constantly, that is, because of the probability that the number of defective bits input and repaired in the column repair circuit 84 is double the number of defective bits before a bus width is widened. Also, the circuit size of the I/O pad 106, for example, the number of pads disposed may increase. With the above description, if a bus width is widened for high-speed ECC processing, a chip size increases to repair defective bits.
Or, the ECC circuit 87 for ECC processing can be configured to be placed in the NAND flash memory 80. For example, there may be considered a semiconductor memory device which uses a part of outputting clear data as an I/O pad by eliminating the I/O pads 106 and 106c with the NAND flash memory 80 and the NAND controller 90 integrated. In this case, if a bus width is widened for high-speed ECC processing, a chip size increases to repair defective bits. Furthermore, since data input in the ECC circuit 87 is data after repairing of defective bits, that is, data passing through the column repair circuit 84, a time for the ECC processing increases as long as a time taken to repair defective bits via the column repair circuit 84.